Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility

ABSTRACT

The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate electrodes and strained Si source/drain regions of P-channel or N-channel transistors, respectively.

FIELD OF THE INVENTION

The present invention relates to micro-miniaturized semiconductordevices comprising transistors on silicon-germanium. The presentinvention is particularly applicable in fabricating transistors withenhanced channel carrier mobility.

BACKGROUND OF THE INVENTION

The relentless pursuit of miniaturized high speed semiconductor devicescontinues to challenge the limitations of conventional semiconductormaterials and fabrication techniques. Conventional semiconductor devicestypically comprise a plurality of active devices in or on a commonsemiconductor substrate, e.g., CMOS devices comprising at least a pairof PMOS and NMOS transistors in spaced adjacency. Current technologyutilizes crystalline semiconductor wafers as substrates, such as alightly p-doped epitaxial (“epi”) layer of silicon (Si) grown on aheavily-doped, crystalline Si Substrate. The low resistance of theheavily-doped substrate is necessary for minimizing susceptibility tolatch-up, whereas the light doping of the epi layer permits independenttailoring of the doping profiles of both the p-type and n-type wellsformed therein as part of the fabrication sequence, thereby resulting inoptimal PMOS and NMOS transistor performance.

The use of the very thin epi layers, i.e., several μm thick, is madepossible by utilizing shallow trench isolation (“STI”), whichadvantageously minimizes up-diffusion of p-type dopant(s) from the moreheavily-doped substrate into the lightly-doped epi layer. In addition,STI allows for closer spacing of adjacent active areas by avoiding the“bird's beak” formed at the edge of each LOCOS isolation structure. STIalso provides better isolation by creating a more abrupt structure,reduces the vertical step from active area to isolation to improve gatelithography control, eliminates the high temperature field oxidationstep that can cause problems with large diameter, i.e., 8 inch, wafers,and is scalable to future logic technology generations.

Substrates based on “strained silicon” have attracted interest as asemiconductor material which provides increased speeds of electron andhole flow therethrough, thereby permitting fabrication of semiconductordevices with higher operating speeds, enhanced performancecharacteristics, and lower power consumption. A very thin, tensilelystrained, crystalline silicon (Si) layer is grown on a relaxed, gradedcomposition of silicon-germanium (Si—Ge) buffer layer several micronsthick, which Si—Ge buffer layer in turn is formed on a suitablecrystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI)wafer. The Si—Ge buffer layer typically contains 12 to 25 at. % Ge.Strained Si technology is based upon the tendency of the Si atoms, whendeposited on the Si—Ge buffer layer, to align with the greater latticeconstant (spacing) of Si and Ge atoms therein (relative to pure Si). Asa consequence of the Si atoms being deposited on a substrate (Si—Ge)comprised of atoms which are spaced further apart, they “stretch” toalign with the underlying Si and Ge atoms, thereby “stretching” ortensilely straining the deposited Si layer. Electrons and holes in suchstrained Si layers have greater mobility than in conventional, relaxedSi layers with smaller inter-atom spacings, i.e., there is lessresistance to electron and/or hole flow. For example, electron flow instrained Si may be up to about 70% faster compared to electron flow inconventional Si. Transistors and IC devices formed with such strained Silayers can exhibit operating speeds up to about 35% faster than those ofequivalent devices formed with conventional Si, without necessity forreduction in transistor size. Conventional practices based on strainedsilicon technology also involve epitaxially growing a relaxed siliconlayer on a tensilely stressed silicon layer which is subsequently dopedto form relaxed source/drain regions in the relaxed silicon layer.

The mobility of electrons is faster than the mobility of holes inconventional bulk silicon substrates. Accordingly, in conventional CMOStransistors, the drive current of the PMOS transistor is less than thedrive current of the NMOS transistor creating an imbalance. Thisimbalance is exacerbated in CMOS transistors fabricated on or within atensilely stressed active device area formed in a strained latticesemiconductor substrate, e.g., strained Si on Si—Ge, because theincrease in electron mobility is greater than the increase in holemobility.

As micro-miniaturization proceeds, there is an attendant need toincrease the drive current of transistors, including transistors formedon various types of strained Si—Ge substrates, by enhancing carriermobility. Accordingly, there exists a need for methodology enabling thefabrication of semiconductor devices comprising transistors formed onSi—Ge substrates with enhanced drive currents by increasing channelcarrier mobility and the resulting semiconductor devices.

DISCLOSURE OF THE INVENTION

An advantage of the present invention is a method of fabricating asemiconductor device comprising transistors on Si—Ge substrates withenhanced drive currents.

Another advantage of the present invention is a semiconductor devicecomprising transistors based on Si—Ge substrates with enhanced drivecurrents.

Additional advantages and other aspects and features of the presentinvention will be set forth in the description which follows and in partwill become apparent to those having ordinary skill in the art uponexamination of the following or may be learned from the practice of thepresent invention. The advantages of the present invention may berealized and obtained as particularly pointed out in the appendedclaims.

According to the present invention, the foregoing and other advantagesare obtained in part by a semiconductor device comprising: a substratecomprising a layer of silicon (Si) having a strained lattice on a layerof silicon-germanium (Si—Ge); a transistor comprising source/drainregions and a gate electrode over the substrate with a gate dielectriclayer therebetween; and a stressed dielectric liner over side surfacesof the gate electrode and over the source/drain regions.

Another advantage of the present invention is a method of manufacturinga semiconductor device, the method comprising: forming a substratecomprising a layer of silicon (Si) having a strained lattice on a layerof silicon-germanium (Si—Ge); forming a transistor comprisingsource/drain regions and a gate electrode, having an upper surface andside surfaces, over the substrate with gate dielectric layertherebetween; and forming a stressed dielectric liner over the sidesurfaces of the gate electrode and over the source/drain regions.

Embodiments of the present invention comprise forming dielectricsidewall spacers on side surfaces of the gate electrode, such as anoxide liner and a nitride layer thereon, epitaxially growing a relaxedSi layer on the strained Si layer, forming source/drain regions in therelaxed Si layer and then depositing the stressed dielectric liner onthe sidewall spacers, on the relaxed source/drain regions and on aportion of the strained Si layer between the sidewall spacers and raisedsource/drain regions.

Embodiments of the present invention also include forming dielectricsidewall spacers on side surfaces of the gate electrode, formingsource/drain regions in the strained Si layer, forming a metal silicidelayer on the upper surface of the gate electrode and a metal silicidelayer on the source/drain regions, removing the dielectric sidewallspacers to expose a portion of the strained Si layer adjacent the sidesurfaces of the gate electrode, and then forming the stress dielectricliner on the metal silicide layer, on the upper surface of the gateelectrode, on the side surfaces of the gate electrode, on the adjacentexposed portions of the strained Si layer, and on the silicide layeroverlying the source/drain regions.

In embodiments of the present invention comprising N-channeltransistors, the stressed dielectric liner exhibits high tensile stress.In embodiments of the present invention comprising P-channeltransistors, the stressed dielectric liner exhibits high compressivestress. The stressed dielectric liner may comprise a layer of siliconnitride, silicon carbide or silicon oxynitride, at a thickness of about200 Å to about 1000 Å.

Embodiments of the present invention include fabricating semiconductordevices comprising complimentary MOS (CMOS) transistors, with acompressive film on the PMOS transistor and a tensile film on the NMOStransistor. According to one aspect of this invention, process flowincludes depositing a compressive stressed nitride film over both theNMOS and PMOS transistors, and then depositing a thin buffer film, suchas an oxide or oxynitride film, over both the NMOS and PMOS transistors.Selective etching is then conducted to remove the oxide and compressivestressed nitride films from the NMOS transistor while masking the PMOStransistor. A tensile stressed nitride film is then deposited over boththe NMOS and PMOS transistors, and then selectively etched away from thePMOS transistor. The resulting CMOS device comprises an NMOS transistorwith a tensile stressed film thereon and a PMOS transistor with acompressive stress film thereon.

Additional advantages and aspects of the present invention will becomereadily apparent to those skilled in the art from the following detaileddescription, wherein embodiments of the present invention are shown anddescribed, simply by way of illustration of the best mode contemplatedfor practicing the present invention. As will be described, the presentinvention is capable of other and different embodiments, and its severaldetails are susceptible of modification in various obvious respects, allwithout departing from the spirit of the present invention. Accordingly,the drawings and description are to be regarded as illustrative innature, and not as limitative.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 schematically illustrate sequential phases of a method inaccordance with an embodiment of the present invention.

FIGS. 3 through 6 schematically illustrate sequential phases of a methodin accordance with another embodiment of the present invention.

FIGS. 7 through 14 schematically illustrate sequential phases of amethod in accordance with another embodiment of the present invention.

In FIGS. 1 and 2, similar features or elements are denoted by similarreference characters; in FIGS. 3 through 6, similar features or elementsare denoted by similar reference characters; and in FIGS. 7 through 14,similar features or elements are denoted by similar referencecharacters.

DESCRIPTION OF THE INVENTION

Transistors built on Si—Ge substrates involve different considerationsthan those built on bulk silicon substrates. Because of the largethickness of silicon substrates, stressed films deposited thereon tendto affect the substrate with a stress opposite to that exhibited by thefilm. For example, if a tensile stressed film is deposited on a bulksilicon substrate, compressive stress is imparted to the substrate and,hence, a channel region. However, typically, and in accordance withembodiments of the present invention, Si—Ge substrates are formed with astrained silicon layer having a thickness of about 200 Å to about 300 Å.Relaxed source/drain regions may be formed thereon at a thickness of upto about 400 Å. Thus, the thickness of the strained Si layer anddrain/source regions together typically does not exceed 800 Å. As aresult, the strained Si layer, even together with a relaxed Si layer, isrelatively transparent to the type of stress exhibited by a filmdeposited thereon. Accordingly, a tensile stressed layer deposited on astrained Si layer, or a relaxed Si layer formed on a strained Si layer,would also impart tensile stress to a channel region formed therein; anda compressive stressed layer deposited on such a thin Si layer or layersimparts compressive stress to a channel region formed therein; whereas,in bulk substrates, the opposite would occur.

The present invention addresses and solves the problem of increasing thedrive current of transistors based on strained Si substrates in a costeffective and efficient manner by significantly enhancing the channelcarrier mobility. The present invention stems from the recognition thatthe channel carrier mobility of transistors based on strained Sisubstrates can be increased by applying a stress thereto. In formingP-channel transistors, channel carrier mobility is enhanced by applyinga stressed dielectric layer exhibiting high compressive stress forincreasing hole mobility. In N-channel transistors, channel carriermobility is significantly increased by applying a stressed layerexhibiting high tensile stress for increasing electron mobility.Stressed dielectric layers may be applied to transistors wherein thesource/drain regions are formed within the strained Si layer, and totransistors having relaxed source/drain regions formed on strained Silayers. The stressed dielectric layer may comprise silicon carbide,silicon nitride or silicon oxynitride, and may be deposited by plasmaenhanced chemical vapor deposition (PECVD) at a thickness of about 200 Åto about 1000 Å. Conventional PECVD conditions may be employed fordeposition of a highly compressive or highly tensile dielectric layer.In depositing a stressed dielectric layer exhibiting high compressivestress, both high frequency and low frequency power are applied. Whendepositing a stressed dielectric layer exhibiting high tensile stress,the low frequency power is significantly reduced. In depositing adielectric layer exhibiting high tensile stress, a tensile stress isapplied to the underlying strained or relaxed Si layer. In applying alayer exhibiting high compressive stress, a compressive stress isapplied to the underlying strained or relaxed Si layer.

For example, a stressed conformal silicon nitride layer exhibiting ahigh compressive stress, e.g., greater than 1 GPa, may be deposited at:a silane (SiH₄) flow rate of 200 to 500 sccm; a nitrogen (N₂) flow rateof 2,000 to 10,000 sccm; an ammonia (NH₃) flow rate of 2,500 to 5,000sccm; a SiH₄/NH₃ ratio of 0.2 to 0.04, a temperature of 350° C. to 550°C.; a pressure of 1 to 6 Torr; a high frequency power of 70 to 300watts; a low frequency power of 20 to 60 watts and an electrode (showerhead) spacing of 400 to 600 mils. A silicon nitride layer exhibiting ahigh tensile stress, e.g., greater than 1 GPa, may be deposited at aSiH₄ flow rate of 50 to 500 sccm; an NH₃ flow rate of 1,500 to 5,000sccm; a N₂ flow rate of 4,000 to 30,000 sccm; a SiH₄/NH₃ ratio of 0.2 to0.04, a temperature of 350° C. to 550° C., a pressure of 2 to 10 Torr; ahigh frequency power of 40 to 300 watts and a low frequency power of 0to 10 watts.

In other embodiments of the present invention, a dielectric layerexhibiting high tensile stress may be formed by depositing thedielectric layer by chemical vapor deposition and then treating thedeposited dielectric layer with ultraviolet or electron beam radiationto increase its tensile stress.

In accordance with embodiments of the present invention, the stressedlayer is applied at a relatively low temperature. Accordingly, thepresent invention enables deposition of a tensile or compressivestressed layer in transistors having nickel silicide layers formed onsource/drain regions and gate electrodes, without exceeding the thermalstability limits of the nickel silicon layers. The present invention isalso applicable to transistors comprising other metal silicides, such ascobalt silicide. In cobalt silicidation, a separate layer of silicon isdeposited prior to depositing a layer of cobalt and implementingsilicidation.

An embodiment of the present invention is schematically illustrated inFIGS. 1 through 6. Adverting to FIG. 1, a layer of strained Si 11 isformed on a layer of Si—Ge 10. It should be understood that Si layer 11may be entirely strained or strained locally in the source/drain regionsas in conventional practices, and that embodiments of the presentinvention encompass both types of strained Si layers. A gate electrode12 is formed over strained Si layer 11 with a gate dielectric layer 13therebetween. Sidewall spacers are then formed comprising an L-shapedoxide liner 14, e.g., silicon oxide, and a nitride layer 15, e.g.,silicon nitride, thereon. A relaxed Si layer 16 is then epitaxiallygrown on strained Si layer 11 and source/drain regions formed therein,as by doping extending the source/drain regions into strained Si layer11. A metal silicide layer 20, 20A, such as nickel silicide, is formedon the upper surface of gate electrode 12 on an relaxed source/drainregion 16, respectively. A stressed dielectric liner 21 is then formedon the sidewall spacers, suicides 20, 20A, and between the oxide liner14 and relaxed source/drain region 16 on the Si layer 11. In embodimentsof the present invention wherein the Si layer is strained locally at thesource/drain regions, the stressed dielectric layer 21 imparts strain 20to silicon layer 11 under the gate electrode and under the spacers,thereby advantageously increasing channel carrier mobility. Inembodiments wherein the entire Si layer 11 is strained, the stresseddielectric layer further increases strain in the channel region underthe gate electrode and spacers, thereby further increasing channelcarrier mobility. Stressed dielectric layer 21 can be, for example,silicon nitride deposited by PECVD exhibiting a high compressive ortensile stress. Additional features illustrated in FIG. 2 includetungsten plug 22 and barrier metal 23, e.g., titanium nitride, fillingan opening in interlayer dielectric 24, and tungsten plug 25 and barriermetal wire 26, such as titanium nitride, filing contact hole 27 ininterlayer dielectric 24. The stress applied by the highly stresseddielectric layer 21 enhances channel carrier mobility, therebyincreasing the drive current of the transistor.

Another embodiment of the present invention is schematically illustratedin FIGS. 3 through 6. Adverting to FIG. 3, strained Si layer 31 isformed over Si—Ge layer 30. As in the previous discussed embodiment, Silayer 31 may be globally strained or locally strained under thesource/drain regions. Gate electrode 32 is formed over strained Si layer31 with a gate dielectric layer 33 therebetween. A sidewall spacercomprising an oxide liner 34, as at a thickness of about 60 Å to about600 Å, is formed on side surfaces of the gate electrode 32 and on aportion of the upper surface of strained Si layer 31. It should beappreciated that liner 34 may be deposited by ALD and may also comprisesilicon nitride. Silicon oxide liner advantageously prevents consumptionof the gate electrode by silicidation on the side surfaces thereof, andadvantageously prevents a subsequently formed thin layer of nickelsilicide on the silicon nitride sidewall spacers from contacting thenickel silicide contact layer on the upper surface of the gate electrodeand/or from contacting the nickel silicide contact layers on the uppersurface of the strained Si layer 31, thereby preventing nickel silicidebridging along the silicon nitride sidewall spacers.

Silicon nitride spacers 35 are then formed on silicon oxide liner 34 asby employing PECVD followed by etching. Subsequently, silicidation isimplemented, as by forming a layer of nickel silicide 40 on the uppersurface of gate electrode 32, as illustrated in FIG. 4, and by forming alayer of nickel silicide 41 on the source/drain region formed in thestrained Si layer 31 or strained portion of silicon layer 31.

As illustrated in FIG. 5, the liner and sidewall spacers are thenremoved exposing a portion of the upper surface of strained Si layer 31between the silicide layers 41 and the side surfaces of gate electrode32, with a very thin oxide layer thereon, e.g., less 50 Å, serving as abuffer layer. A highly stressed dielectric layer 50 is then deposited,such as a silicon nitride layer exhibiting high compressive stress, byPECVD, as shown in FIG. 6. The highly stressed dielectric layer 50serves to increase channel hole mobility, thereby increasing the drivecurrent.

Another embodiment of the present invention is schematically illustratedin FIGS. 7 through 14. Adverting to FIG. 7, a CMOS device isschematically illustrated comprising an NMOS transistor portion at theleft and a PMOS transistor portion on the right, wherein similarfeatures are denoted by similar reference characters. Strained Si layer71 is formed over Si—Ge layer 70. As in previous discussed embodiments,Si layer 71 may be globally strained or locally strained in thesource/drain regions. Gate electrode 72 is formed over strained Si layer71 with a gate dielectric layer 73 therebetween. A sidewall spacercomprising an oxide liner 74, as at a thickness of about 60 Å to about600 Å, is formed on side surfaces of gate electrode 72 and on a portionof the upper surface of strained Si layer 71. Silicon oxide liner 74 canbe formed in the same manner as discussed with respect to silicon oxideliner 34 in FIG. 3. Silicon nitride spacers 75 are then formed onsilicon oxide liner 74, as by employing PECVD followed by etching.Subsequently, silicidation is implemented, as by forming a layer ofnickel silicide 76 on the upper surface of gate electrodes 72 and byforming a layer of nickel silicide 77 on the source/drain regions formedon the strained Si layer 71.

As illustrated in FIG. 8, liner 74 and sidewall spacer 75 are removedfrom each transistor exposing a portion of the upper surface of strainedSi layer 71 between silicide layers 77 and the side surfaces of gateelectrode 72. A highly compressive stressed silicon nitride film 90,having a compressive stressed greater than 1.5 GPa, is then depositedover both the NMOS and PMOS transistors as illustrated in FIG. 9.Deposition of highly compressive stressed silicon nitride film 90 may beimplemented at a temperature of about 400° C. to about 480° C., at aSiH₄ flow rate of about 200 to about 300 sccm, an NH₃ flow rate of about3,000 to about 4,000 sccm, a N₂ flow rate of about 3,500 to about 4,500sccm, a pressure of about 2 to about 6 Torr, a shower head spacing ofabout 400 to about 600 mils, a high frequency RF power of about 60 toabout 100 watts, a low frequency RF power of about 40 watts to about 90watts, followed by NH₃/N₂ plasma treatment with NH₃ at a flow rate ofabout 500 to about 1500 sccm and with N₂ at a flow rate of about 2,000to about 4,000 sccm, at a high frequency RF power of about 100 watts toabout 600 watts, and a low frequency RF power of about 20 watts to about60 watts for about 20 to about 60 seconds. Multiple layer deposition andplasma treatment further increases compressive stress. Subsequently, athin oxide or oxynitride film 100 is deposited, as illustrated in FIG.10, by a conventional CVD process. Typically oxide or oxynitride film100 is deposited at a thickness of about 30 Å to about 60 Å.

Subsequently, a mask 110, e.g., photoresist or hard mask is applied overthe PMOS transistor, as illustrated in FIG. 11, and the oxide oroxynitride film 100 and high compressive stress silicon nitride film 90removed from the NMOS transistor.

Adverting to FIG. 12, the mask 110 is removed from the PMOS transistor,a highly tensile stressed silicon nitride film 120, having a tensilestress of greater than 1.5 GPa, is then deposited over both the PMOS andNMOS transistors. Deposition of highly tensile stressed film 120 can beimplemented at a temperature of about 400° C. to about 480° C., a SiH₄flow rate of about 40 to about 80 sccm, and NH₃ flow rate of about 1,500to about 2,500 sccm, a N₂ flow rate of about 20,000 to about 40,000sccm, a spacing (between substrate and shower head) of about 400 toabout 600 mils, a pressure of about 2 to about 8 Torr, a high frequencypower of about 40 to about 80 watts, and a low frequency power up toabout 10 watts. A thin oxide or oxynitride film 130 is then deposited bya conventional CVD process, as at a thickness of about 30 Å to about 60Å.

Adverting to FIG. 13, a mask 131, such as a photoresist or hard mask, isthen applied over the NMOS transistor, and the oxide or oxynitride film130 and the highly tensile stressed silicon nitride film 120 areselectively removed from the PMOS transistor stopping on the oxide oroxynitride film 100. The mask 131 is then removed, and the resultingstructure is illustrated in FIG. 14 which comprises an oxide oroxynitride film 130 and a highly tensile stressed silicon nitride film120 over the NMOS transistor and an oxide or oxynitride film 100 and ahighly compressive stressed silicon nitride film 90 over the PMOStransistor. The resulting CMOS device comprises both PMOS and NMOStransistors with increased channel carrier mobility and, hence,increased drive current.

The present invention provides methodology enabling the fabrication ofhigh quality, high operating speed, micro-miniaturized semiconductordevices based upon strained lattice technology, with maximizedtransistor drive currents. The inventive methodology can be practicedutilizing conventional processing techniques and instrumentalities atrates consistent with the throughput requirements of automatedfabrication techniques, and is fully compatible with conventionalprocess flow for the manufacture of high-density integratedsemiconductor devices.

The present invention enjoys industrial applicability in fabricatingvarious types of semiconductor devices. The present invention enjoysparticular industrial applicability in fabricating micro-miniaturizedsemiconductor devices with high operating speeds.

In the previous description, numerous specific details are set forth,such as specific materials, structures, reactants, processes, etc., inorder to provide a better understanding of the present invention.However, the present invention can be practiced without resorting to thedetails specifically set forth. In other instances, well-knownprocessing materials and techniques have not been described in detail inorder not to unnecessarily obscure the present invention.

Only the preferred embodiment of the present invention and but a fewexamples of its versatility are shown and described in the presentdisclosure. It is to be understood that the present invention is capableof use in various other combinations and environments and is susceptibleof changes or modifications within the scope of the inventive concept asexpressed herein.

1-9. (canceled)
 10. A method of manufacturing a semiconductor device,the method comprising: forming a substrate comprising a layer of silicon(Si) having a strained lattice on a layer of silicon-germanium (Si—Ge);forming a transistor comprising source/drain regions and a gateelectrode, having an upper surface and side surfaces, over the substratewith a gate dielectric layer therebetween; and forming a stresseddielectric liner over the side surfaces of the gate electrode and overthe source/drain regions, wherein the strained Si layer is eitherglobally strained or locally strained in the source/drain regions. 11.The method according to claim 10, comprising: forming a sidewall spaceron the side surfaces of the gate electrode; epitaxially growing arelaxed layer of Si on the strained Si layer; forming source/drainregions in the relaxed Si layer; and depositing the stressed dielectricliner on the sidewall spacers, on the relaxed source/drain regions andon portions of the strained Si layer between the sidewall spacers andrelaxed source/drain regions, wherein the stressed dielectric linercomprises a layer of silicon nitride, silicon carbide or siliconoxynitride at a thickness of about 200 Å to about 1000 Å.
 12. The methodaccording to claim 10, comprising forming dielectric sidewall spacers onthe side surfaces of the gate electrode by: depositing an oxide liner onthe side surfaces of the gate electrode and on a portion of the strainedSi layer adjacent the side surfaces of the gate electrode; anddepositing a nitride layer on the oxide liner.
 13. The method accordingto claim 12, comprising: forming the source/drain regions in thestrained Si layer; forming a first metal silicide layer on the uppersurface of the gate electrode and a second metal silicide layer on thesource/drain regions; removing the dielectric sidewall spacers exposinga portion of the strained Si layer adjacent the side surfaces of thegate electrode; and forming the stressed dielectric liner on the firstmetal silicide layer, on the side surfaces of the gate electrode and onthe adjacent exposed portions of the strained Si layer.
 14. The methodaccording to claim 13, wherein the transistor is a P-channel transistor,the method comprising forming the stressed dielectric layer bydepositing a dielectric layer by plasma enhanced chemical vapordeposition under conditions such that it exhibits high compressivestress.
 15. The method according to claim 13, wherein the transistor isan N-channel transistor, the method comprising forming the stressdielectric liner by plasma enhanced chemical vapor deposition under suchconditions that it exhibits high tensile stress.
 16. The methodaccording to claim 13, wherein the transistor is an N-channeltransistor, the method comprising forming the stress dielectric linerby: depositing a dielectric layer; and treating the dielectric layersuch that it exhibits high tensile stress.
 17. The method according toclaim 16, comprising treating the dielectric layer with ultraviolet orelectron-beam radiation such that it exhibits high tensile stress.
 18. Amethod of fabricating a semiconductor device, the method comprising:forming a substrate comprising a layer of silicon (Si) having a strainedlattice on a layer of silicon-germanium (Si—Ge); forming CMOStransistors comprising an NMOS transistor and a PMOS transistor, eachtransistor comprising source/drain regions and a gate electrode, havingan upper surface and side surfaces, over the substrate with a gatedielectric layer therebetween; forming sidewall spacers on the sidesurfaces of each gate electrode; forming metal silicide layers on theupper surface of each gate electrode and on the surface of thesource/drain regions of each transistor; removing the sidewall spacersfrom the side surfaces of each of the gate electrodes; depositing alayer of silicon nitride exhibiting high compressive stress over theNMOS and PMOS transistors; depositing an oxide or oxynitride liner onthe silicon nitride layer exhibiting high compressive stress;selectively removing the oxide or oxynitride liner and silicon nitridelayer exhibiting high compressive stress from the NMOS transistor;depositing a layer of silicon nitride exhibiting high tensile stress onthe NMOS transistor; and on the PMOS transistor; and depositing an oxideor oxynitride liner on the silicon nitride layer exhibiting high tensilestress on the NMOS transistor and PMOS transistor, and selectivelyremoving the oxide or oxynitride liner and the silicon nitride layerexhibiting high tensile stress from the PMOS transistor.
 19. The methodaccording to claim 18, comprising: depositing the layer of siliconnitride exhibiting high compressive stress; depositing the layer ofsilicon nitride exhibiting high tensile stress by plasma enhancedchemical vapor deposition at a temperature of 400° C. to about 480° C.;and forming layers of nickel silicide as the metal silicide layers. 20.The method according to claim 18, comprising depositing the layer ofsilicon nitride exhibiting high compressive stress by depositingmultiple layers with intervening plasma treatment in ammonia andnitrogen.